1. Field
Embodiments described herein relate generally to a non-volatile semiconductor storage device.
2. Description of the Related Art
Conventionally, electrically rewritable non-volatile semiconductor storage devices (EEPROM) are known. Among others, NAND cell type flash memory has been widely used since it allows for a high level of integration. The NAND cell type flash memory includes NAND cell units (memory strings), each having a plurality of memory cells connected in series so that source/drain diffusion layers are shared among adjacent cells. MOS transistors are used as memory cells of the NAND cell type flash memory. The MOS transistors include electric charge accumulation layers (floating gates) and control gates laminated and formed on a semiconductor substrate. The memory cells store data in a non-volatile manner depending on the amount of electric charges accumulated in the floating gates. There has also been proposed such NAND cell type flash memory that uses MONOS cells including electric charge accumulation layers of silicon nitride films or the like, instead of floating gates.
Each NAND cell unit has one end connected via a select gate transistor to a bit line, and the other end connected via a select gate transistor to a source line. The control gate of each memory cell is connected to a word line. A set of a plurality of memory cells formed along one word line forms one page (where 1 bit is stored per cell) or a plurality of pages (where multiple bits are stored per cell) on which a data write or read operation is performed simultaneously.
In addition, a plurality of NAND cell units aligned in the word-line direction are included in one block, which is usually a unit of collective data erase. Moreover, one plane includes a plurality of block arranged along the bit-line direction. Furthermore, for so-called multi-chip modules, multiple memory chips can be mounted on a single memory card.
In such NAND cell type flash memory, with recent advances in miniaturization and increasing demand for larger capacity, more and more memory chips are included in one module and the size of one page becomes larger and larger. Moreover, this leads to an increase in the number of memory cells connected in series in one NAND cell unit. Under these circumstances, there is an increase in the data volume of address data input at the time of reading and writing data.
Furthermore, if a multi-value storage scheme is adopted to store multiple bits of data (multiple pages of data) in one memory cell, then the address of the page in question must be specified.
Therefore, the data volume of address data tends to increase in association with an increase in memory capacity and adoption of multi-value storage schemes. As such, the larger the the data volume of address data becomes, the longer it will take to transfer the data. This may affect the operating speed of memory cells.